Перевод: с русского на все языки

со всех языков на русский

verification level

См. также в других словарях:

  • Verification (spaceflight) — Verification in the field of space systems engineering covers two verification processes: Qualification and Acceptance Overview Verification standards are developed by organizations like the NASA and the ECSS to establishes the requirements for… …   Wikipedia

  • Verification and Validation (software) — In software project management, software testing, and software engineering, Verification and Validation (V V) is the process of checking that a software system meets specifications and that it fulfils its intended purpose. It is normally part of… …   Wikipedia

  • Current sea level rise — This article is about the current and future rise in sea level associated with global warming. For sea level changes in Earth s history, see Sea level#Changes through geologic time. Sea level measurements from 23 long tide gauge records in… …   Wikipedia

  • Device driver synthesis and verification — The device driver is a program which allows the software or higher level computer programs to interact with a hardware device. These software components act as a link between the devices and the operating systems, communicating with each of these …   Wikipedia

  • National technical means of verification — is a phrase that first appeared, but was not detailed, in the Strategic Arms Limitation Treaty (SALT) between the US and USSR. At first, the phrase reflected a concern that the Soviet Union could be particularly disturbed by public recognition of …   Wikipedia

  • Functional verification — Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question Does this proposed design do what is… …   Wikipedia

  • Mechanism for Cooperation and Verification — The Mechanism for Cooperation and Verification (CVM) is safeguard measure invoked by the European Commission in case some new member or acceding state of the European Union has failed to implement commitments undertaken in the context of the… …   Wikipedia

  • Electronic system level — (ESL) design and verification is an emerging electronic design methodology that focuses on the higher abstraction level concerns first and foremost. It is defined in the ESL Design and Verification book [Brian Bailey, Grant Martin and Andrew… …   Wikipedia

  • Self-verification theory — For self testing in electronics, see built in self test Self verification is a social psychological theory that asserts people want to be known and understood by others according to their firmly held beliefs and feelings about themselves, that is …   Wikipedia

  • High-level synthesis — (HLS), sometimes referred to as C synthesis, electronic system level (ESL) synthesis, algorithmic synthesis, or behavioral synthesis, is an automated design process that interprets an algorithmic description of a desired behavior and creates… …   Wikipedia

  • Asic verification — is today’s most challenging problem for ASIC designers. As chip sizes have skyrocketed and use of IP has increased, the need to fully verify the design functionality has become critical. However, verification is a function of both design size and …   Wikipedia

Поделиться ссылкой на выделенное

Прямая ссылка:
Нажмите правой клавишей мыши и выберите «Копировать ссылку»